As integrated circuit geometries associated with CMOS imaging arrays continue to shrink, power distribution presents significant challenges. Typically, the CMOS imaging array is organized as a rectangular array of rows and columns of pixel sensors. During readout, all of the pixel sensors in a given row are read out in parallel by column processing circuitry. There are thousands of such columns, and the voltages on each column and the bias currents through the bit lines must be the same. As the feature size is reduced, the voltages that can be used to operate the CMOS array must also be reduced. In addition, the sizes of conductors that distribute the power must be reduced. The reduced conductor sizes make it difficult to maintain constant voltages across all of the columns when current is flowing.